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VLSI Design for Video Coding

H.264/AVC Encoding from Standard Specification to Chip
Lin, Youn-Long Steve/Kao, Chao-Yang/Kuo, Hung-Chih et al
ISBN/EAN: 9781441909589
Umbreit-Nr.: 1287179

Sprache: Englisch
Umfang: xi, 176 S.
Format in cm:
Einband: gebundenes Buch

Erschienen am 12.02.2010
Auflage: 1/2010
€ 106,99
(inklusive MwSt.)
Lieferbar innerhalb 1 - 2 Wochen
  • Zusatztext
    • High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing. This book will present VLSI architectural design and chip implementation for high definition H.264/AVC video encoding, using a state-of-the-art video application, with complete VLSI prototype, via FPGA/ASIC. It will serve as an invaluable reference for anyone interested in VLSI design and high-level (EDA) synthesis for video.
  • Kurztext
    • Back Cover Copy VLSI Design for Video Coding By: YounLong Lin ChaoYang Kao JianWen Chen HungChih Kuo High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing. This book presents VLSI architectural design and chip implementation for high definition H.264/AVC video encoding with a complete FPGA prototype. It serves as an invaluable reference for anyone interested in VLSI design for video coding. Presents stateoftheart VLSI architectural design and chip implementation for high definition H.264/AVC video encoding; Employs massively parallel processing to deliver 1080pHD, with efficient design that can be prototyped via FPGA; Every subsystem is presented from standard specification, algorithmic description, design considerations, timing planning, block diagram to testbench verification;