Detailansicht
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
eBook
ISBN/EAN: 9783319023786
Umbreit-Nr.: 9279596
Sprache:
Englisch
Umfang: 0 S., 6.66 MB
Format in cm:
Einband:
Keine Angabe
Erschienen am 19.11.2013
Auflage: 1/2013
E-Book
Format: PDF
DRM: Digitales Wasserzeichen
- Zusatztext
- This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.<br>
- Kurztext
- This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
- Autorenportrait
- Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.