Detailansicht
Digital Phase Lock Loops
Architectures and Applications
ISBN/EAN: 9781441941053
Umbreit-Nr.: 1586469
Sprache:
Englisch
Umfang: xviii, 192 S.
Format in cm:
Einband:
kartoniertes Buch
Erschienen am 29.10.2010
Auflage: 1/2007
- Zusatztext
- InhaltsangabePreface. Acronyms. 1 General Review of Phase-Locked Loops. 1.1 Overview of Phase-Locked Synchronization Schemes. 1.2 The Synchronization Challenge. 1.3 Phase-Locked Loops. 1.3.1 Analog Phase-locked Loops. 1.3.2 PLL Basic Components. 1.3.3 PLL analysis. 1.4 Conclusions. 2 Digital Phase Lock Loops. 2.1 Introduction. 2.2 Classification of DPLLs. 2.3 Conclusion. 3 The TimeDelay Digital Tanlock Loops (TDTLs). 3.1 Introduction. 3.2 Structure and System Equation. 3.2.1 Structure of the TDTL. 3.2.2 System Equation. 3.2.3 The Characteristic Function. 3.3 System Analysis. 3.3.1 Firstorder TDTL. 3.3.2 Secondorder TDTL. 3.4 Convergence Behavior of the TimeDelay Digital Tanlock Loop. 3.4.1 Convergence Behavior. 3.5 Conclusions. 4 Hilbert Transformer and Time-Delay. 4.1 Introduction. 4.2 Statistical Behavior of HT and Time-Delay in i.i.d. Additive Gaussian Noise. 4.2.1 Input-Output Relationships in the Presence of Noise. 4.2.2 Joint PDF of the Amplitude and Phase Random Variables. 4.2.3 PDF of the Phase Random Variable. 4.2.4 PDF of the Phase Noise. 4.2.5 Expectation and Variance of the Phase Noise. 4.2.6 The phase Estimator and Ranges of Cramer-Rao Bounds. 4.2.7 A Symmetric Transformation. 4.3 Conclusions. 5 The Timedelay Digital Tanlock Loop in Noise. 5.1 Introduction. 5.2 Noise Analysis of the TDTL. 5.2.1 System Equation. 5.2.2 Statistical Behavior of TDTL Phase Error Detector. 5.2.3 Phase Estimation and CramerRao Bounds. 5.2.4 Statistical Behavior of the TDTL in Gaussian Noise. 5.3 Conclusions. 6 TDTL Architectures for Improved Performance. 6.1 Introduction. 6.2 Simulation Results of First-Order TDTL. 6.3 Improved First-Order TDTL Architectures. 6.3.1 Delay Switching Architecture. 6.3.2 Adaptive Gain Architecture. 6.3.3 Combined Delay Switching and Adaptive Gain. 6.3.4 Sample Sensing Adaptive Architecture. 6.3.5 Early Error Sensing Adaptive Architecture. 6.4 Simulation Results of Second-Order TDTL. 6.5 Improved Second-Order TDTL Architectures. 6.5.1 Adaptive Filter Coe_cients Second Order TDTL. 6.5.2 Adaptive Loop Gain Second-Order TDTL. 6.6 Variable Order TDTL Architecture. 6.7 Conclusions. 7 FPGA Reconfigurable TDTL. 7.1 Overview of Reconfigurable Systems. 7.2 FPGA Structure and Operation. 7.3 Xtreme DSP Development System. 7.4 TDTL FPGA Implementation. 7.4.1 The CORDIC Arctangent Block. 7.4.2 The Digital Controlled Oscillator. 7.4.3 The CORDIC Divider. 7.5 Real-Time TDTL Results. 7.5.1 First-Order TDTL. 7.5.2 Second-order TDTL. 7.5.3 Sample Sensing Adaptive TDTL. 7.6 Conclusions. 8 Selected Applications. 8.1 PM Demodulation Using the First-Order TDTL. 8.2 Performance in Gaussian Noise. 8.3 Simulation Results. 8.4 FSK and FM Demodulation. 8.5 Wideband FM Signal Detection. 8.6 Conclusions. Bibliography. Index.
- Kurztext
- A wide coverage of digital phase lock loops including a new class called TDTLTheoretical and practical aspects of digital phase lock loopsFPGA-based reconfigurable implementation of digital phase lock loop architecturesSelected applications of digital phase lock loopsIncludes supplementary material: sn.pub/extras
- Autorenportrait
- Prof. Al-Araji received the B.Sc., M.Sc., and Ph.D. degrees from the University of Wales Swansea, (UK), all in electrical engineering in 1968, 1969, and 1972 respectively. Since September 2002, Professor Al-Araji was appointed Professor and Head of Communications Engineering Department at Etisalat University College (Emirates Telecommunication Cooperation), Sharjah, UAE. Prior to that and for six years he was working at the Transmission Network Systems, Scientific-Atlanta, Atlanta, Georgia, USA as Senior Staff Electrical Engineer. During the academic year 1995/1996, Prof. Al-Araji was visiting professor at the Ohio State University, Columbus, Ohio, USA. He was visiting professor at King's College, University of London, England, during the summers of 1988 and 1989. Prof. Al-Araji was professor and Department Head at the University of Baghdad, Iraq, and the University of Yarmouk, Jordan. Prof. AlAraji was awarded the British IERE Clerk Maxwell Premium for a paper published in 1976 and the ScientificAtlanta award for outstanding achievement in the year 2000. He was an Iraqi National member of URSI Commissions C and D, and the ITU (CCIR Group 8). His research interests include synchronization techniques, communication signal processing, and CATV systems and networks. He has published over 50 papers in international Journals and Conferences and holds 6 US Patents and one International Patent. He is a reviewer to a number of international conferences and journals, and is involved in the organization of a number of international conferences in various capacities. Prof. AlAraji is a senior member of the IEEE. His email address is: alarajis@euc.ac.ae.